Flat-panel displays are widely used for portable computers such as laptop and notebook personal computers (PCs). Super-twisted nematic (STN) liquid-crystal displays (LCDs) are relatively inexpensive. To increase the contrast ratio of these displays, the amount of time pixels are driven on or off, and the overall duty cycle is decreased by splitting the display into two halves. Each of these two halves is independently driven so that two rows of pixels are illuminated at any instant in time.
Additional memory, called a half-frame buffer (HFB), is used to store pixels driven to the split display. The incoming pixels are sent to both the half-frame buffer and one half of the display. Once all pixels for the display-half are sent, then the buffer drives the same pixels to that display half, while pixels for the other display-half are received by the buffer and simultaneously sent to the other display half. Thus two streams are simultaneously sent to the display--one stream for each display-half.
FIG. 1 is a diagram of a prior-art display system using a half-frame buffer. Pixel pipeline 12 receives a stream of pixels from a frame-buffer memory (not shown) and converts these pixels for display by cathode-ray tube (CRT) 10. Colors may be re-mapped by pixel pipeline 12 and attributes such as blinking cursors added. The pixel stream to CRT 10 is tapped off and sent to gray-scale converter 14 for display on a flat panel LCD.
Unlike CRTs, some flat-panel displays such as Dual-STN LCD's are single-bit digital devices that can only display a pixel as fully on or fully off. CRTs are analog devices that can display shades of pixels by increasing or decreasing the intensity of a displayed pixel or its color components. Gray-scale converter 14 converts multi-bit pixel intensities for an analog display to single-bit digital (on or off) pixels. The digital on/off pixels are sent directly to upper panel-half 20 and to half-frame buffer 16. Half-frame buffer 16 simultaneously sends buffered pixels for lower panel-half 22.
Once all pixels for upper panel-half 20 have been sent and stored by half-frame buffer 16, then pixel connections are swapped and half-frame buffer 16 drives the buffered pixels to upper panel-half 20, while the incoming pixels from gray-scale converter 14 are sent to lower panel-half 22. These incoming pixels are also stored in half-frame buffer 16.
Storage space is freed in half-frame buffer 16 as the buffered pixels are sent to upper panel-half 22. Thus a total storage of about one-half a frame of pixels is required for half-frame buffer 16. The pixels sent to half-frame buffer 16 do not have to be identical to the pixels simultaneously sent to the flat panel. Instead, pixels from the next frame can be sent to half-frame buffer 16 while pixels from the current frame are sent directly to the panel. This results in frame acceleration, since double the number of flat-panel frames are displayed for each CRT frame. Flicker is reduced.
Three Half-Frame Buffers--FIG. 2
FIG. 2 is a prior-art graphics system using three half-frame buffers. Calculating row and column data applied to a flat-panel display may be complex, requiring that the last frame of data be stored for use in calculations. Prince in U.S. Pat. No. 5,617,113, assigned to In Focus Systems of Wilsonville Oreg., discloses storing the entire last frame of data in addition to the current half-frame buffer. Memory requirements are reduced from two complete frames to one and a half frames using Prince's system, although a non-conventional, multi-bit-pixel frame-rate cycling (FRC) scheme is used.
Incoming pixels are gray-scale converted and routed to one of three half-frame buffers 24, 26, 28. These buffers may be read (not shown) during gray-scale calculations. Multiplexers 31, 33 each select converted pixels from one of half-frame buffers 24, 26, 28 for display on panel-halves 20, 22. At any point in time, one of half-frame buffers 24, 26, 28 is receiving incoming data, while another buffer is sending pixels to upper panel-half 20 while the remaining buffer is sending data to lower panel-half 22. Buffers 24, 26, 28 rotate their functions after each half-frame of pixels is received.
The complex calculations made in this prior-art scheme use three half-frame buffers, or 1.5 frames of memory. Only 2x frame acceleration is achieved using 1.5 frames of memory. Thus memory efficiency is less than standard techniques that achieve the same frame acceleration.
A common gray-scaling technique is known as frame-rate cycling (FRC). A pixel's shading is approximated by blinking the pixel on and off over a cycle of several frames. For example, a 50% gray can be approximated by turning the pixel on for one frame, but off for the next frame. The gray-scale converter can send an on pixel directly to the display, but write an off pixel to the half-frame buffer for display in the next frame.
Technology is improving the response speed of the liquid-crystal fluid in an LCD panel. Faster LCD fluid allows better rendition of rapidly-moving images encountered with multimedia movie clips and animations. Unfortunately, with the faster LCD fluid the contrast ratio becomes worsened and the grayscale flicker becomes noticeable. To counteract these problems with fast LCD fluids, these displays can be refreshed at faster rates, improving image quality. Pixel data can be sent to these displays at higher rates. While simply buffering pixel data and re-transmitting it at the higher rates improves the contrast ratio, it does not reduce flicker. Generating many frames of gray-scale data could result in large memory-storage use. Improved techniques are desired that take advantage of the faster flat-panel displays, yet are memory-efficient.
What is desired is a graphics system for high-bandwidth and high-refresh-rate flat-panel displays. It is desired to use frame-rate-cycling gray-scaling, but minimize the memory required for buffering. More efficient data-handling techniques and timing are desired.